A venture in retrotronics
Open-source RISC processors making waves in research and industry
It's still early in terms of silicon implementations, tooling and operating system support, but the open RISC-V processor specification is making inroads in the processor world. As RISC-V Marketing Manager Ted Marena wrote at the beginning of last year on IEEE Times, RISC-V is to open hardware what Linux has been to open-source software.
According to Naveed Sherwani, the CEO of SiFive, today's complex chips are so expensive to develop that the situation for the chip industry is unhealthy:
The cost of developing a chip is so high that no VCs will fund it and no young people will try it.
To research institutes, startups and government agencies involved in High-Performance Computing (HPC), and to bulk consumers of processing power, RISC-V provides an opportunity to participate and collaborate in creating a (European) technical and scientific ecosystem around an open design.
RISC-V is an open-source Instruction Set Architecture (ISA) specification. Everything required to create a CPU based on this instruction set and use it to run actual operating systems and applications is available as open source software [1, 2].
More specifically, RISC-V is supported by gcc/gdb and LLVM, while Segger has included support for RISC-V in its Embedded Studio. SiFive has published Freedom Studio, a development environment (IDE) built on top of Eclipse. Early operating system support is available for Linux (in Debian and Fedora), FreeBSD and NetBSD.
One notable implementation of RISC-V is the PULP platform, a joint research project by ETH Zurich in Switzerland and the University of Bologna in Italy on the energy efficiency of microprocessor architectures. Based entirely on open-source hardware and software, the project has resulted in the tape-out of two dozen implementations. You can read more on PULP here.
Another implementation has been created by commercial company SiFive, which is offering various RISC-V-based chips and boards. Cofounder of SiFive is Krste Asanović, who is also Chairman of the Board of the RISC-V Foundation and the inventor of the RISC-V architecture.
There are dozens of others projects based on RISC-V [1, 2], some of them quite far-reaching. For example, GPU manufacturer nVidia is looking to replace its embedded Falcon processor with RISC-V. And Western Digital is looking to use RISC-V in its storage products. This company expects to ship over one billion RISC-V processors per year.
The RISC-V Foundation aims to further the development of the RISC-V specification and its adoption. Next to semiconductor companies – startups as well as established firms – and research organisations, a lot of the more than one hundred members are bulk consumers of CPUs or processing power, for example Alibaba, Bitmain, Google, Hitachi, Huawei, IBM, nVidia, Samsung, Seagate, Siemens, and Western Digital.
Notable absentees from this list are market leaders Intel and ARM, though Intel is one of the investors in SiFive through its Intel Capital division.
Strikingly, last summer ARM launched the website 'riscv-basics.com' (no longer available) as part of a smear campaign against RISC-V. The effort quickly backfired and ARM had to take the site down within days to prevent further damage, even from its own employees. Of course this reminds us of the Fear, Uncertainty and Doubt (FUD) campaigns Microsoft used to run against open-source software.
RISC-V has it origins in academic research on Instruction-Level Parallelism (ILP) in the 1990s. The DLX is a pipelined RISC architecture developed by John Hennessy and David Patterson as part of their courses in computer architecture and the main production in their classic textbook 'Computer Architecture: A Quantitative Approach'. Earlier this year the two computer scientists won the ACM Turing Award for their contributions to microprocessor architecture design. The DLX was turned into concrete chip designs – some of them open source – but never into an actual product. Patterson has been involved in the development of RISC-V and is Vice Chair of the Board of Directors of the RISC-V Foundation.
The year 2000 yielded the OpenRISC processor design – as the name implies, another open RISC architecture, this one aimed at embedded computer systems (System on Chip, SoC). The main difference from the DLX architecture is the incorporation of SIMD instructions to natively support multimedia. OpenRISC is supported by gcc/gdb and Linux.
OpenRISC was initially hosted by the OpenCores community, but in 2015 it migrated away to the LibreCores platform of the newly established Free and Open Source Silicon Foundation (FOSSi Foundation) after a falling out with the owners of OpenCores. FOSSi is the organiser of the annual ORConf open source digital design conference.
The OpenRISC 1200 design was written in Verilog by OpenCores cofounder Damjan Lampret and published under the LGPL licence. It was implemented as ORPSoC on FPGA hardware, and has been used in several commercial derivatives.
An OpenRISC-based Linux computer was launched into space in 2012 as part of the NASA TechEdSat programme. In addition to Linux and the GNU toolchain, OpenRISC is supported by several Real-Time Operating Systems (RTOSes).
An improved, more recent implementation of the OpenRISC 1000 series ISA is the mor1kx core, written by Stefan Kristiansson and Julius Baxter and published under the Open Hardware Description License (OHDL).
Just like in the software world, commercial companies have made proprietary ISA specifications and digital designs available to the general public by publishing them under open-source licences. When it comes to CPUs, the best example is OpenSPARC, the name under which Sun Microsystems (now Oracle) in 2006 published the Verilog code of its UltraSPARC processor under the GPL licence. A few processors were built on this design, though it no longer appears to be topical.
ESA's research centre ESTEC has made its own implementation of the SuperSPARC ISA (UltraSPARC's predecessor) in VHDL and published it under the (L)GPL licence. These LEON processors were specifically developed for use in the European space programme and are supported by almost a dozen RTOSes. In this case a licence from Sun was not required, as the SPARC V8 ISA is an open IEEE standard.
Despite its name, OpenPOWER is not an open processor architecture; it's the name of IBM's programme for licensing specifications and tooling for its high-end RISC Power Architecture to its partners through the OpenPOWER Foundation.
Advantages of open-source hardware
Open-source hardware has advantages very similar to those of open-source software. It allows others to reuse and build on existing IP cores, or collaboratively share the costs of Non-Recurring Engineering (NRE). As one Twitter user put it: "The good thing about working with open source hardware designs is not to have free designs available to grab, but to have someone else to work with to improve a design together."
A great example is Wishbone, a topologically adaptable computer bus to interconnect the various IP cores on a chip. It has become the de facto standard for open-source hardware, and guarantees the interoperability of the various parts.
Another example is FuseSoC, a package manager and build tool for HDLs, currently comprising more than 100 hardware designs.
European Processor Initiative
RISC-V is one of the two processors – the other one being ARM – selected for the European Processor Initiative (EPI). This project aims to develop the low-power microprocessor and various accelerators that eventually will power European exascale supercomputers. To this end, a consortium of 23 European organisations from research and industry has been established, and EUR 120 million is expected to be invested through the Horizon 2020 research programme.
EPI is part of the European High-Performance Computing Joint Undertaking (EuroHPC), which aims to acquire and deploy two world-class supercomputers (exascale) and at least two mid-range supercomputers (pre-exascale). The idea is to build a European HPC ecosystem and stimulate European research and innovation in HPC, putting Europe on a par with the USA, China and Japan. The EU will contribute EUR 486 million, the participating countries will add a similar amount, and industry partners will invest more than EUR 400 million, making a total of EUR 1.4 billion.
In the meantime US Defence research agency DARPA is pouring a similar amount (USD 1.5 billion) into the automation of chip design. DARPA's Electronics Resurgence Initiative (ERI) aims to develop methods and tooling to churn out processor topologies and hardware accelerators for application-specific workloads. One of the programmes, named POSH (Posh Open Source Hardware), aims to create an open-source SoC design and verification ecosystem that will enable the cost-effective design of ultra-complex SoCs.